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r03ds0061ej0200 rev.2.00 page 1 of 11 jul 24, 2013 preliminary datasheet R2A20135SP led lighting power controller description r2a20135 is led lighting controller ic with dimming function. high accuracy led current feed-back system makes more efficient led performance. with non-isolation step-down control makes it possible to reduce external parts and realize high power factor and efficiency. moreover, this ic builds in the dimming function and can control many types dimming mode such as triac, pwm, and dc dimming. switching mode can chosen zero current detect mode or fixed frequency mode according to the required features. by the constant on time control, both modes have power factor correct function. zero current detect mode is better performance for noise immunity, and fixed frequency mode is for power factor correction and thd. features ? absolute maximum ratings ? supply voltage vcc: 24 v ? operating junction temperature tjopr: ?40 to +150c ? electrical characteristics ? uvlo operating start voltage vh: 12 v 0.8 v ? uvlo operating shutdown voltage vl: 9.2 v 0.7 v ? uvlo hysteresis voltage hysuvl: 2.8 v 0.7 v ? functions ? dimming function (triac, pwm, dc dimming) ? zero current detection mode (when rrt is open) ? fixed frequency mode (when rrt is connected by gnd) ? adjustable switching frequency (w hen rrt is connected by gnd) ? package lineup: pb-free sop-8 (jedec) ordering information part no. package name package code package abbreviation taping abbreviation (quantity) R2A20135SP#w5 ? prsp0008dj-a sp w (2,500 pcs/reel) r03ds0061ej0200 rev.2.00 jul 24, 2013
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 2 of 11 jul 24, 2013 pin arrangement (top view) fb 1 comp 2 rt 3 fb+ vcc out gnd pwm 4 8 7 6 5 pin function pin no. pin name input/output function 1 fb input error amplifier input pin 2 comp output error amplifier output pin 3 rt input/output a resistor connec tion pin for ramp current setting 4 fb+ input/output a conducto r connection pin for pwm voltage stability and dc dimming 5 pwm input input pwm signal 6 gnd ? ground 7 out output power mosfet drive pin 8 vcc input supply voltage pin
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 3 of 11 jul 24, 2013 block diagram uvlo off: 9.2 v/on: 12 v vref: 5.02 v 30 a 0.204 v error amp 2.7 v/2.5 v 1 v pwm vref 0.75 a vref 1 v ramp control logic block u rrt: open (zero current detection mode) u rrt: connect to gnd (fixed frequency mode) 2 comp 1 fb 4 fb+ 5 pwm 8vcc 6gnd 7out 3rt 8 mv ? + ? + + ? + ? + + ? 1 a 0.5 a 10 pf 4.1 v 4 v uvlo off: 9.2 v/on: 12 v vref: 5.02 v 30 a 0.204 v error amp 2.7 v/2.5 v 1 v pwm vref 0.75 a vref 1 v ramp control max duty detect logic block 2 comp 1 fb 4 fb+ 5 pwm 8vcc 6gnd 7out 3rt ? + + ? 1 v + ? 2 v + ? + ? + + ? 10 pf 4.1 v 4 v rr t
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 4 of 11 jul 24, 2013 absolute maximum ratings (ta = 25c) item symbol ratings unit note power supply voltage vcc ?0.3 to +24 v fb pin voltage vt-fb ?0.3 to +5 v comp pin voltage vt-comp ?0.3 to +5 v rt pin voltage vt-rt ?0.3 to +5 v fb+ pin voltage vt-fb+ ?0.3 to +5 v pwm pin voltage vt-pwm ?0.3 to +5 v out pin peak current ipk-snk-out 0.9 a 3 ipk-src-out ?0.50 out pin dc current idc-snk-out 100 ma idc-src-out ?50 rt pin current irt ?200 to +100 a pwm pin current ipwm 500 a power dissipation pt 0.68 w 4 operating junction temperature tjopr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. rated voltages are wi th reference to the gnd pin. 2. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 3. shows the transient current when driving a capacitive load. 4. in case of R2A20135SP: ja = 120c/w this value is a thing mounting on 40 40 1.6 [mm], a glass epoxy bo ard of wiring density 10%.
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 5 of 11 jul 24, 2013 electrical characteristics (ta = 25c, vcc = 15 v, fb = comp, rrt = 200 k ) item symbol min typ max unit test conditions supply uvlo turn-on threshold vuvlh 11.2 12 12.8 v uvlo turn-off threshold vuvll 8.5 9.2 9.9 v uvlo hysteresis hysuvl 2.1 2.8 3.5 v standby current istby ? 130 200 a vcc = vuvlh ? 0.2 v operating current i cc ? 2.2 3.3 ma error amplifier feedback voltage vfb 0.194 0.204 0.214 v *3 minimum feedback voltage vfb_min ? 0 ? mv input bias current ifb ?50 ?30 ?15 a vfb = 13 mv open loop gain av ? 63 ? db upper clamp voltage vclamp_comp 3.85 4.10 4.30 v fb = 0 v comp: open low voltage vl-comp ? 0.9 ? v fb = 0.4 v comp: open source current isrc-comp ?14 ?9 ?5 a fb = 0 v comp = 2.5 v sink current isnk-comp 12 20 27 a fb = 1 v comp = 2.5 v transconductance gm 25 45 70 s fb = 0.15 v ? 0.25 v comp = 2.5 v zero current detector zcd threshold voltage vzcd 2 8 14 mv restart restart time delay tstart 45 75 140 s fb = 0 v, comp = 2.5 v, rt = open rt ramp offset voltage voffset_ramp ? 1.0 ? v ramp amplitude dvramp 2.9 3.1 3.3 v *2 rt voltage1 v-rt1 1.9 2.0 2.1 v rt-gnd: 200 k rt bias current irt ?0.7 ?0.5 ?0.2 a rt = 2.5 v pwm maximum input frequency fpwm_max ? ? 100 khz *1 input bias current ipwm ?0.35 ?0.75 ?1.5 a upper clamp voltage vclamp_pwm 3.5 4.0 4.5 v clamp current = 100 a pwm high threshold voltage vr_pwm 2.40 2.70 3.00 v pwm low threshold voltage vf_pwm 2.25 2.5 2.75 v fb+ minimum output voltage vfb+_lo ? 0 10 mv vpwm = 0 v out rise time tr-out ? 30 100 ns cl = 1000 pf fall time tf-out ? 30 100 ns cl = 1000 pf out low voltage vol1-out ? 0.08 0.20 v isink = 20 ma vol2-out ? 0.05 0.70 v isink = 10 ma, vcc = 5 v out high voltage voh-out 14.5 14.8 ? v isource = ?20 ma out frequency fout 43 48 53 khz rt-gnd: 200 k maximum duty cycle dmax 47 52 57 % rt-gnd: 200 k notes: * 1 design spec * 2 dvramp = vclamp_comp ? voff_ramp * 3 there is the possibility of change for the standard value.
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 6 of 11 jul 24, 2013 waveforms (zero current detection mo de/fixed frequency mode common) 1. start-up timing (zero current detection mode/fixed frequency mode common) comp fb out vref vcc 12 v (vuvlh) 5.02 v 3.6 v vref good (internal signal) 1 v 0.9 v 2. stop timing (zero current detection mode/fixed frequency mode common) out normal operation vcc 9.2 v (vuvll)
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 7 of 11 jul 24, 2013 3. gate drive output (zero current detection mode) ramp+1v (internal signal) ramp (internal signal) fb out il 8 mv comp 0 a cs out comp il zero current detect zoom-up 0.8 s 8 mv ramp+1v (internal signal) ramp (internal signal) 0 a
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 8 of 11 jul 24, 2013 4. gate drive output (fixed frequency mode) 4.1 error amp control mode cs 0 v 0 a 2 v 1 v max duty 50% ramp+1v (internal signal) ramp (internal signal) out il comp 5. pwm characteristics 0 pwm on duty (%) pwm on duty (%) fb+ (v) 0.87 3.23 error amp ref. (v) 0.204 17 65 100 0 17 65 100
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 9 of 11 jul 24, 2013 system diagram 1. step-down fixed frequency mode 1.1 non dimming to q from d from out c1 l1 d1 q1 to fb and cs d ri1 d2 z1 ccomp comp fb vcc fb+ gnd pwm out rt rrt + rcs ri2 d3 q filter 1.2 triac dimming iout to q from d from out c1 l1 d1 q1 to fb and cs d ri1 d2 z1 ccomp comp fb vcc fb+ gnd pwm out rt rrt cfb+ + rcs ri2 d3 q filter
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 10 of 11 jul 24, 2013 2. step-down zero current detection mode 2.1 non dimming to q from d from out c1 l1 d1 q1 to fb and cs d ri1 d2 z1 ccomp comp fb vcc fb+ gnd pwm out rt + rcs ri2 d3 q filter 2.2 triac dimming iout to q from d from out c1 l1 d1 q1 to fb and cs d ri1 d2 z1 ccomp comp fb vcc fb+ gnd pwm out rt cfb+ + rcs ri2 d3 q filter
R2A20135SP preliminary r03ds0061ej0200 rev.2.00 page 11 of 11 jul 24, 2013 package dimensions note) 1. dimensions"*1 (nom)"and" *2" do not include mold flash. 2. dimension"*3"does not include trim offset. 0.10 1.27 0.56 5.84 6.20 0.410.35 4.98 max nom min 4.80 3.99 3.81 dimension in millimeters symbol reference 1.73 0.890.640.41 3.94 1.47 0.25 0.150.10 0.49 0.250.20 0.19 5.99 8 0 0.25 1.03 4.93 e h e l a d e a 2 a 1 b p b 1 c x y z l 1 c 1 previous code jeita package code renesas code prsp0008dj-a ? mass[typ.] 0.073g p-sop8-3.94x4.93-1.27 c terminal cross section (ni/pd/au plating) detail f l 5 8 4 f *1 *2 *3 mx 1 index mark s s y a d e z e l 1 a 1 b p b p h e
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